| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 140 | --------------------------- Authors:........................ |
............ |
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| IJVDCS 141 | Reducing Area and Delay of FIR Filter using by Digit Serial Multiplier Methodology Authors:KUNREDDY VIDHYA DHARI, S.N CHANDRA SHEKHAR |
0778-0781 |
Download | |
| IJVDCS 142 | Design and Implementation of Pseudo Random Number Generator Used in AES Algorithm Authors:M. SRIKANTH, SANDEEP SUNKARI |
0782-0786 |
Download | |
| IJVDCS 143 | Design of Approximation Adders used in Future DSP Processor Authors:K.TIRUPATI, PRASHANT PISE, K. ASHOK BABU |
0787-0793 |
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| IJVDCS 144 | Design of CLAA, CSLA and PPA based Shift and Add Method Multiplier Authors:JAGARLAMUDI G NARENDRA, B. SRINIVAS, K. ASHOK BABU |
0794-0798 |
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| IJVDCS 145 | Design and Implementation of VECLIW Architecture for Executing Multi-Scalar Instructions Authors:POTHUGANTI ABDUL SHAREEF, M.SOWJANYA, K.ASHOK BABU |
0799-0802 |
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| IJVDCS 146 | Design of Novel Full Adder for Future Processors Authors:SHAHEN SYED, S.VIJAYA LAXMI |
0803-0806 |
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| IJVDCS 147 | Implementation of Image fusion by Lifting DWT using Micro-blaze Processor Authors:CH. SHARATH KUMAR, D. KOTESHWAR RAO |
0807-0811 |
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| IJVDCS 148 | Human Motion Detection Based on Background Subtraction Authors:UJJWAL V.S, K. MALLIKARJUNA LINGAM |
0812-0816 |
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| IJVDCS 149 | Design of Dual Dynamic Node Flip-Flop with an Embedded Logic Design Authors:K. SRAVANI, UDAY SRI, K.ASHOK BABU |
0817-0823 |
Download | |
